Yhey are iterations so we never got to know the exact cpu type. We've only observed that they changed around about 2000 and can run some options with less alignment to avoid crashes. There is a file MPC500_M68300_CD_ZIP.zip (yes exactly like that) that you can get from NXP here https://www.nxp.com/...

I feel like this was already determined however I cannot seem to find the answers. Was it determined what primary CPUs were in the P10 and P12 that controls the flash memory? I am trying to trace out the boot and JTAG pins and I need to know so I can look at the correct CPU pinout. I did post pics f...

I still have the boards from the P10 and P12 that I dismantled to help PCM Hammer development of the P10 and the P12. Maybe I can take a look at these boards and pins off the CPUs for both and come up with something that I can test.

NSFW wrote: ↑Wed May 07, 2025 2:20 pm Thanks for doing all of that testing!

No problem at all. I am happy to contribute in any way that I can.

I tested all of the compatible PCMs that I have at the moment with the new PCM Hammer 2.0 preview, and I have organized all of the results according to PCM model. All PCMs for one model are zipped into the folder named according to the model and then organized further individually. Download each fil...

I am watching this closely Antus. I have been trying to understand the ins and outs of USB JTAG and BDM, and I am hoping someone comes along with some answers.

I am curious to know the answers to this as well...

Has there been any more progress on this cool project?

Very cool. I have been out of the loop for a little bit and I am trying to get caught up. I will have to test a bunch of my PCMs on the bench and see how it goes.

Very cool. I am willing to help also if needed.