Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

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Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby antus » Sun Jun 05, 2016 6:13 pm

As I have been working on a VPW interface lately, I have had the need to see whats going on with the data bus. I have the vpw specs, but in reality there is differing timing between different devices, and I have found even the same device depending on low or high logic levels.

So I purchased a dslogic pro analyser which includes software based on the open source sigrok project which includes the ability to do software protocol decode in python.

VPW was not supported, so I have written and open sourced such a decoder. It is available at the link below which is directly to the main source file.

https://bitbucket.org/antuspcm/sigrok-v ... ew-default

Below are some screen shots. You might need to click a couple of times to expand the images to see all the content. You can see it auto detects VPW 1x or 4x based on the duration of the Start Of Frame (SOF) byte, and then uses appropriate timings to decode the rest of the packet. It does this on a packet by packet basis, so it can follow whats going on even when bus speed is switched.

Most sigrok decoders do not display timing information like this decoder does, but I found the real world timings to be very useful for my purposes so I left them it in.
Attachments
1x frame.png
4x frame start.png
4x frame partial zoom out.png
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Re: Sigrok/dsview logic analyser - VPW 1x and 4x decoder too

Postby ejukated » Sun Jun 05, 2016 7:10 pm

Very cool! Thanks for sharing

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Re: Sigrok/dsview logic analyser - VPW 1x and 4x decoder too

Postby jenko » Sun Jun 05, 2016 7:40 pm

above my head but love it

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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby pman92 » Thu Apr 30, 2020 8:32 pm

Hi Antus
I've got a cheap logic analyser and sigrok pulseview on windows 10 and I'm wondering how to actually install/use your decoder

Is it just a matter of putting the "vpw" folder containing the 2 python files in the directory with all the other decoders?
C:\Program Files (x86)\sigrok\PulseView\share\libsigrokdecode\decoders

Or is there more involved? Because I've put it in there but there is no VPW decoder listed in PulseView

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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby antus » Thu Apr 30, 2020 8:41 pm

Yes thats right, but there is probably some version or api dependancy on versions. If you can find a way to get python to syntax check the file, or see stdout when sigrok trys to run the decoder you might get a clue. It shouldnt take much to get it running if you can see the debug output. When I wrote it on dsview i couldnt see errors and I had to run it after every tiny change and if I got nothing back assume i'd broken it and start guessing why. Surely sigrok is better to develop for than dsview was, and you can mayby run it from the cli maybe with a debug switch and see what python says when you choose the decoder in the UI. I would be interested to help getting it in sigrok if I can. The official dev team never picked it up but i'd like to see it in the project.
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby pman92 » Thu Apr 30, 2020 9:09 pm

Antus it looks like your on the money.
I've got really no idea what I'm doing and I'm in over my head. BUT using your information I downloaded sigrok-cli and installed it, and put the "vpw" folder in it's corresponding "libsigrokdecode/decoders" directory as well.

Running sigrok-cli.exe from the command line I found the option -L to list everything supported.
When I run "sigrok-cli.exe -L", under the "Supported protocol decoders" list that is outputted I get the following 2 lines:

srd: Only PD API version 3 is supported, decoder vpw has version 2.
srd: Failed to load decoder vpw: API version mismatch

I'm guessing its an easy fix but I know nothing about python.

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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby antus » Thu Apr 30, 2020 9:23 pm

Maybe try and identify and see if you can use the last version that suports decoder api v2. The changes to api 3 look like a redesign. It wouldnt be impossible but you'd need to get your head around python, how sigrok work works and the plugin to do it. Alternatively you might be able to find in the sigrok repository a commit that changes one of the more simple protocol decoders from v2 to v3 and try and apply the same on the vpw.
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby pman92 » Thu Apr 30, 2020 9:58 pm

It seems support for version 2 was dropped in 2018

There's a few commits listed here changing from version 2 to version 3

https://sigrok.org/gitweb/?p=libsigrokd ... code-0.5.x

I might see if I can get my head around it and make it work
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby pman92 » Fri May 01, 2020 7:53 am

Ok I have modified the pd.py file in the same way I can see a bunch of other decoders were modified to change from version 2 to version 3 API.

It now seems I can use the decoder in sigrok-cli, although I'm not sure its completely working properly.
However it's still not listed in PulseView (even after copying the changed pd.py file over to it's "libsigrokdecode/decoders" directory)

I have saved a short .sr file of a small amount of VPW data that I captured with my cheap logic analyzer using PulseView (found it easier to setup in PulseView than sigrok-cli).
I can then use that file as an input for sigrok-cli and specify to use the vpw decoder, and I get this output:

Code: Select all
C:\Program Files (x86)\sigrok\sigrok-cli>sigrok-cli -i C:\Users\dprie\OneDrive\Desktop\sample.sr -P vpw
vpw-1: 41 ns
vpw-1: 41 ns
vpw-1: 228 ╬╝s
vpw-1: 64 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 41 ns
vpw-1: 41 ns
vpw-1: 127 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 41 ns
vpw-1: 83 ns
vpw-1: 63 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 125 ns
vpw-1: 41 ns
vpw-1: 127 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 64 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 41 ns
vpw-1: 166 ns
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 41 ns
vpw-1: 41 ns
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 41 ns
vpw-1: 41 ns
vpw-1: 128 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 8 ms
vpw-1: 228 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 41 ns
vpw-1: 125 ns
vpw-1: 157 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 41 ns
vpw-1: 41 ns
vpw-1: 64 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 64 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 64 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 63 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 93 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 157 ╬╝s
vpw-1: 128 ╬╝s
vpw-1: 41 ns
vpw-1: 41 ns
vpw-1: 93 ╬╝s
vpw-1: 127 ╬╝s
vpw-1: 157 ╬╝s

C:\Program Files (x86)\sigrok\sigrok-cli>


I guess it's partly working but not completely

Attached in the .zip is the modified pd.py and the sample data .sr I captured
Attachments
vpw.zip
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder

Postby pman92 » Fri May 01, 2020 7:56 am

Heres the data open in PulseView, and no option for the vpw decoder in the list:

PulseView.png
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