V6 ability for pcm hammer.

They go by many names, P01, P59, VPW, '0411 etc . Circa 1999 to 2006. All VPW OBD2 PCMs.
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Re: V6 ability for pcm hammer.

Postby antus » Wed Jan 15, 2020 10:47 am

Thats not really what i mean. Its more, what happens when someone flashes and amd os on an intel p59, or vice-versa? how do they flash the pcm from then on, if the kernel cant detect which hardware it is? But this is the v6 thread. Similar problems though, we'll be up against different chip types, I think.
Have you read the FAQ? For lots of information and links to significant threads see here: viewtopic.php?f=7&t=1396

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Re: V6 ability for pcm hammer.

Postby Vampyre » Wed Jan 15, 2020 10:57 am

ahh ok got yeah now, I was thinking do the file checks program side before allowing flash. even my tech 2 wont write a p59 intel or amd with opposing file. learned that hardway, had to go find correct pcm for a customer

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Re: V6 ability for pcm hammer.

Postby Vampyre » Wed Jan 15, 2020 11:39 am

For future reference where is flash is stored?

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Re: V6 ability for pcm hammer.

Postby antus » Wed Jan 15, 2020 11:52 am

What do you mean, the flash?
Have you read the FAQ? For lots of information and links to significant threads see here: viewtopic.php?f=7&t=1396

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Re: V6 ability for pcm hammer.

Postby Gampy » Wed Jan 15, 2020 11:53 am

Vampyre wrote:Hardware wise only 2 dif hardware numbers for P01 files are interchangable
P59 same 2 hardware numbers files not interchangeable
P04 2 hardware numbers ive ever seen all files interchangeable.

Ive got a tech2 if you want I can load different OS into pcms and see if it changes anything

Vampyre wrote:ahh ok got yeah now, I was thinking do the file checks program side before allowing flash. even my tech 2 wont write a p59 intel or amd with opposing file. learned that hardway, had to go find correct pcm for a customer

Vampyre,

I assure you, older OS's from the P04 cannot be run on a newer P04, at this point in time I do not know what Os's will and will not, but I do know that the 2000 Grand Am GT file you uploaded will not run on my 2005 P04.
That file came from a Intel flash unit prior to the appearance of the AMD Flash chip, My 2005 has an AMD flash chip.

Ok, I see you got to your PM, It will report it is a AMD chip, that may or may not be correct, doesn't matter they are both 512k and that is all that matters at this point.

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Re: V6 ability for pcm hammer.

Postby Vampyre » Wed Jan 15, 2020 12:12 pm

antus wrote:What do you mean, the flash?



flash ID not flash is, stupid typos

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Re: V6 ability for pcm hammer.

Postby antus » Wed Jan 15, 2020 12:22 pm

Well its stored in ram at runtime, and sent back to pcmhammer which logs it, i think the debug logs. You should see it in the main log or debug log tab from any flash with pcmhammer. Thats it.
Have you read the FAQ? For lots of information and links to significant threads see here: viewtopic.php?f=7&t=1396

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Re: V6 ability for pcm hammer.

Postby Gampy » Wed Jan 15, 2020 12:32 pm

Vampyre wrote:flash ID not flash is, stupid typos

The flash ID is retrieved from the Flash Chip itself upon request by PcmHammer.

This is the Intel Flash Chip Identification code used by the kernel.
Code: Select all
uint32_t Intel_GetFlashId()
{
   SIM_CSBAR0 = 0x0006;
   SIM_CSORBT = 0x6820;

   // flash chip 12v A9 enable
   SIM_CSOR0 = 0x7060;

   // Switch the flash into ID-query mode
   FLASH_BASE = SIGNATURE_COMMAND;

   // Read the identifier from address zero.
   uint32_t id = FLASH_IDENTIFIER;

   // Switch back to standard mode
   FLASH_BASE = READ_ARRAY_COMMAND;

   SIM_CSOR0 = 0x1060; // flash chip 12v A9 disable

   return id;
}

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Re: V6 ability for pcm hammer.

Postby antus » Wed Jan 15, 2020 1:28 pm

everything in caps is a #define, so look at the h files to see what that expands to, but it implements the magic in the flash datasheet in a nice readable way.
Have you read the FAQ? For lots of information and links to significant threads see here: viewtopic.php?f=7&t=1396

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Re: V6 ability for pcm hammer.

Postby 160plus » Wed Jan 15, 2020 1:51 pm

@Gampy

I don't get on these forums much so emailing me would be the best way to contact me if your interested.

This would likely require a significant amount of restructuring in Pcm Hammer but your welcome to use the flash kernels I developed with Kur4o(from Gearhead efi) for Ls Droid. I have read and write kernels that will support 1x speed and a custom multi part flash loader that adds mode 80 multi part upload support for the V6 computers. I'm pretty sure the flash loader is small enough that even the ODBLink Sx would be able to load it but I haven't looked at the size in quite some time, I know it works just fine with the Lx/Mx it's just that the Sx has a slightly smaller buffer.

The read routine is going to work the same as what PCM hammer uses and it supports flash chip ID for the 256K chips as well as the 512K Intel and AMD chips. I know the write kernel works on both the Intel and AMD 512K chips but I'd have to talk to Kur4o to see if he ever did any testing with it on a 256K. Now....the write kernel doesn't work in the same manner as the PCM hammer or I'm sure someone would have already made a version that used Ls Droid kernels by now. I know it CAN be made to work with PCM Hammer, I half ass hacked a write kernel for the P01 into PCM Hammer a long time ago and I'm pretty sure my hacked up version is what NSFW used to recover his 0411 after he accidentally erased the calibration data and put the PCM into recovery mode. I'm not a C programmer and what I did wasn't pretty but it did work... so if someone that knew what they were doing wanted to put the time into doing it "the right way" I'd be happy to give them some Ls Droid kernels to use.

I'm not sure how much of the flash chip you've already mapped out but there is no inbuilt recovery mode on these computers, after bricking several computers we made some pretty radical changes to how the write kernel worked that completely solved the issue....but some feel what we did in the kernel was a bit over the top, either way I have multiple versions of the V6 write kernel that are all fully functional. The other real issue with these computers is the calibration data shares a section of the flash chip with OS Data so a conventional calibration flash isn't possible.... technically your supposed to reflash the entire chip any time you make a change to the bin file. But lets face it, 1x speeds make that very time consuming so we also came up with a way to add calibration flashing but it's a rather unconventional method that took some thinking outside the box to come up with.

I found almost zero interest in V6 flashing with Ls Droid, so little in fact that the number of people who wanted to "test" the V6 read/write wasn't enough to make me comfortable releasing it to the public. So it'd be a shame to just sit on everything I spent months working on for these pcm's when someone else is interested in them. The only thing I would ask for in return was for a copy of the Pcm Hammer source code after the kernels were added and working.


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