Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
Antus, I've given up on fixing it myself as I've got no idea what I'm doing.
I reached out to some people on the #sigrok IRC chat (https://webchat.freenode.net/). They seem VERY interested in getting it working and included.
They suggested I clone the libsigrokdecode repo, add your 2016 version PD and commit changes, then do other changes I have done to try and get it working and commit them as well. Then connect the clone with a github account, provide the URL to the public repo in the IRC chat, and they can review and suggest changes.
The problem is I'm not very familiar with git because I've never really used it
They also requested I get plenty of example captures: "example captures go to the sigrok-dumps repo (another clone which you'd amend), see existing directories for README files that should accompany the .sr files"
There is also a new page on their wiki: https://sigrok.org/wiki/Protocol_decoder:J1850_vpw and they've given me a wiki account and asked me to add to it. If you ask for an account on their IRC chat they will give you one as well.
I reached out to some people on the #sigrok IRC chat (https://webchat.freenode.net/). They seem VERY interested in getting it working and included.
They suggested I clone the libsigrokdecode repo, add your 2016 version PD and commit changes, then do other changes I have done to try and get it working and commit them as well. Then connect the clone with a github account, provide the URL to the public repo in the IRC chat, and they can review and suggest changes.
The problem is I'm not very familiar with git because I've never really used it
They also requested I get plenty of example captures: "example captures go to the sigrok-dumps repo (another clone which you'd amend), see existing directories for README files that should accompany the .sr files"
There is also a new page on their wiki: https://sigrok.org/wiki/Protocol_decoder:J1850_vpw and they've given me a wiki account and asked me to add to it. If you ask for an account on their IRC chat they will give you one as well.
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
Thats awesome! I actually ordered a generic $20 logic analyser today to look at this. The dslogic is dead. Dont know when i'll get a chance but i'd like to see this across the line, and im keen to help.
You should link this thread on the wiki page. Thanks
You should link this thread on the wiki page. Thanks
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
I think I've worked out github just enough to get this done (first time I've ever had anything to do with my own repo)
https://github.com/pman92/libsigrokdeco ... coders/vpw
https://github.com/pman92/sigrok-dumps/tree/master/vpw
And I've also updated the wiki page
https://github.com/pman92/libsigrokdeco ... coders/vpw
https://github.com/pman92/sigrok-dumps/tree/master/vpw
And I've also updated the wiki page
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
This will just be a side project when i'm board so I make no promises about how long, if at all, I get there. But the hardware arrived, and 'hello world'.
Have you read the FAQ? For lots of information and links to significant threads see here: http://pcmhacking.net/forums/viewtopic.php?f=7&t=1396
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
@pman92 Ive pushed your changes in to a develop branch on bitbucket because thats whereit was, I dont mind if it ends up on github, and maybe eventaually I'll move that and a few other projects in to the same repo as pcmhammer. I will start having a play with this.
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
I managed to get it loading in pulseview, but I cant figure out why the debug level switch -l 5 produces no output. Or if it does, where that output goes. The decoder throws an error so its not full ported yet, but its closer. It ended up just needing whitespace fixes, and a reset function which calls init.
https://bitbucket.org/antuspcm/sigrok-v ... ea125ad974
Edit: Found it! In the gui
https://bitbucket.org/antuspcm/sigrok-v ... ea125ad974
Edit: Found it! In the gui
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
time channel is now working, getting close
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
Awesome work antus
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Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
Antus what a machine haha good to see you still can't put something down once you get a taste haha
If Its Got Gas Or Ass Count Me In.if it cant be fixed with a hammer you have an electrical problem
Re: Sigrok/dsview logic analyser J1850 VPW 1x 4x decoder
Careful, you'll get hooked and wonder how you ever got along without it!pman92 wrote:I think I've worked out github just enough to get this done (first time I've ever had anything to do with my own repo)
I say, Linus finally did something worthwhile, he instructed his team to create git.
That's cool Antus.
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