Emotions, you bet, I am very passionate about my work, I devote a lot of time to it and take it very seriously, it is me, it's my face, it makes me whom I am.
I'm just trying to get this resolved as well, but you are making statements and changes that are 100% incorrect and make absolutely no sense at all.
My gawd, can't you wait a few months, at least until I'm dead!
When I tell you what you need to do, it is ignored, which is evident in the irrelevant and or incorrect changes you continue to make.
I can't make headway if I have to keep cleaning up behind you and wasting time defending my work all because you do not have time to do your due diligence and homework.
It goes with my mantra, what goes in, comes out, thus garbage in, garbage out, or intelligence in, intelligence out ...
I have spent the last two years fairly steady (some breaks here and there to allow soak in) studying M68k Assembly, I have been through a M68k course, I have worked through Motorola tutorials as well as Intel and AMD materials, I have probably 1000 to 1500 commits of my testing and playing to understand all matters of things involving various parts of this process.
All those commits are me doing my homework, figuring out how things like the DBcc instructions unroll, so I know how to properly and accurately use them.
And I've done this with all the core instructions and some pertinent directives, I do not care about most features, I have zero desires to code for vehicles.
My interests are strictly reading and writing flash.
You say you are an RE, I say I'm a wanna be programmer ... How about we do this.
You do the disassembly work and let me do the assembly work!
You want technical descriptions of what I do and why in English, please do so, let us start with the big white elephant in your work, register d0 and why it all of a sudden broke causing you to not understand why you needed to change it to register d7 ... ??AMD??
Code: Select all
IntelFlashUnLock:
.
. Wacked for brevity
.
| Enable +12v Vpp
#if defined P04
clr.w %d0 | P04 needs this syntax <<<<<<<<<<<<<<<<<<<<<<<<-- Because you are overwriting it (the count)!
bset #VPP_BIT, %d0 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<-- Because you are overwriting it (the count)!
move.w %d0, (HARDWARE_IO).w <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<-- Because you are overwriting it (the count)!
#elif defined P08
bset #VPP_BIT, (HARDWARE_IO).w | P08 needs this syntax
#else
move.w (HARDWARE_IO).w, %d1 | Move Vpp Latch Address value to d1
bset #VPP_BIT, %d1 | Set Vpp Latch Bit
move.w %d1, (HARDWARE_IO).w | Move modified value back to Latch Address
#endif
Code: Select all
IntelFlashLock:
.
. Wacked for brevity
.
| Disable +12v Vpp
#if defined P04
clr.w %d0 | P04 needs this syntax <<<<<<<<<<<<<<<<<<<<<<<<<-- Because you are overwriting it (the return code)!
move.w %d0, (HARDWARE_IO).w <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<-- Because you are overwriting it (the return code)!
#elif defined P08
bclr #VPP_BIT, (HARDWARE_IO).w | Does not work on P01, needed for P08
It's obviously not going to work correctly with the byte count being overwritten between the time it's loaded into the register and used, and the return code cleared ...
As I have stated many times before the P04 does not require that construct in the first place, it works perfectly with the construct under #else.
Thus, changes just to make changes with nothing to back them up ...
Do your homework, RTFM, do proper testing.
Are the following bugs, yes, are they harmful, no, not really, but they are incorrect that's for sure ...
As my comment stated that you removed, there is no need for this sub, it is only needed in one place. You not only removed the comment, you incorrectly followed the clear usability comment in the first place creating one of the next red flags that shows how much homework you have not done.
Code: Select all
LongWaitWithWatchdog:
movem.l %d5, -(%sp) | Save d5 <<<<<<<<<<<<<<<<<<<-- RTFM
move.w #0x8000, %d1 | 32768 loops <<<<<<<<<<<<<<<-- ONE OFF ERROR (Mostly irrelevant in this case), it's actually 32769 loops, thus poor timing math as is!
LongWaitLoop:
bsr.w ResetWatchdog | Scratch the dog
bsr.w WasteTime | Twiddle thumbs
dbf %d1, LongWaitLoop | If False Decrement and Branch
movem.l (%sp)+, %d5 | Restore d5 <<<<<<<<<<<<<<<<-- RTFM
rts
Using hex for counts and indexes is human error prone for one off errors, not to mention most compilers/preprocessors convert them to decimal.
Now I know this isn't harmful, my point is, I have fixed multiples of your one off bugs due to this, that and alignment is also the original works main downfall!
Again, changes just to make changes with nothing to back them up ...
Code: Select all
IntelEraseSector:
.
. Wacked for brevity
.
IntelEraseSectorNotReady:
bsr.w LongWaitWithWatchdog <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<-- Poor design!
move.w #READ_STATUS_REGISTER, (%a0) | 0x7070 Read Status Register <<<<<<<<<<<<<<<<<<<-- RTFM
move.w (%a0), %d1 | Move Status to d1
btst #0x007, %d1 | Test Status
bne.s IntelEraseSectorReady | Status Success - Jump to IntelEraseSectorReady
subq.l #1, %d2 | Decrement index
bne.s IntelEraseSectorNotReady | Fail Status Check Test again
First off, it's a Wait For loop, having a delay in a wait for loop is poor design, increase the timeout to accommodate, and allow it to finish according to the performance of the current unit.
I was taught that delays are typically the sign of poor code design, split the process up with other processes in between them ... however, sometimes that is not possible and delays are required.
In this case, A delay is required after enabling Vpp, and ONLY WHEN ENABLING IT ... Therefore the sub LongWaitWithWatchdog is nothing more then bloat!
Again, well proven unnecessary changes, plus logically unnecessary.
Code: Select all
IntelFlashLock:
.
. Wacked for brevity
.
#endif
bsr.w LongWaitWithWatchdog <<<<<<<<<<<<<<<<<<<<<-- It's done, this does nothing but slow the process down for zero reasons!
rts
Again, making changes just to make changes with nothing to back them up ...
-Enjoy