pcmhacking.net

kojab wrote:One thing to look out for is the supply voltage while re-flashing the OS with this type of PCM. If the Voltage drops under approx 12 volts you can brick the PCM. Check your bench harness voltage with ignition on. I like to see 13.8 volts. Never bricked one yet.

When CE# and RP# pins are at VCC, the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode
which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are
recognized. See Section 4.2.
The deep power-down mode can also be used as a device reset, allowing the flash to be reset along
with the rest of the system. For example, when the flash memory powers-up, it automatically defaults
to the read array mode, but during a warm system reset, where power continues uninterrupted to the
system components, the flash memory could remain in a non-read mode, such as erase.
Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read
mode upon activation of the Reset signal. This also provides protection against unwanted command
writes due to invalid system bus conditions during system reset or power-up/down sequences.

RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to control two different functions: reset/deep power-down mode and boot block unlocking. It is backwards-compatible with the BX/BL/BV products.

evilstuie wrote:I found this on the Intel data sheet for the chip, but still decyphering all this foreign tech terminology into english:

When CE# and RP# pins are at VCC, the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode
which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are
recognized. See Section 4.2.
The deep power-down mode can also be used as a device reset, allowing the flash to be reset along
with the rest of the system. For example, when the flash memory powers-up, it automatically defaults
to the read array mode, but during a warm system reset, where power continues uninterrupted to the
system components, the flash memory could remain in a non-read mode, such as erase.
Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read
mode upon activation of the Reset signal. This also provides protection against unwanted command
writes due to invalid system bus conditions during system reset or power-up/down sequences.

And the definition for the #RP pin:

RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to control two different functions: reset/deep power-down mode and boot block unlocking. It is backwards-compatible with the BX/BL/BV products.

I still don't think these will give me an answer on their own, even if I manually apply voltage or grounding (still not sure which for which) to these during power up, I think your software would still need to manually force flash the bin on yes?

I'm looking at buying a TL866A flasher and desoldering the chip to see if i can read it and what happened exactly, but I don't think I'll have the skill and coordination to solder the chip back on.
At least if I can do this i can flash the chip with the correct OS, then solder back onto the PCM

evilstuie wrote:Still waiting for the programmer to arrive, I'll let you know.