pcmhacking.net

Actually, it looks like the MCU has a separate 16 bit address bus and 8 bit data bus - it's just not using the address bus, the ram, eprom etc all appear to be on the multiplexed D bus.
So it might be possible to wire a standard eprom (or NVRAM even) directly up to the processor...

LMAO, it's sounds amazing but... It's all double dutch to me!

I have what I think is a more defined PDF for MCU process called EECTEC10 but I have no idea what it means!

Can u please stop wasting your time I'm sure you have more important things to keep you busy!!!

Just noticed the long spiel to try & explain...

It sort of confused me but I do understand sort of!

But again it all sounds too difficult & don't want you to waste your time on it!

VX L67 Getrag wrote: I have what I think is a more defined PDF for MCU process called EECTEC10 but I have no idea what it means!

Here's how that pdf describes a read on the multiplexed bus - pretty much as I guessed earlier:

On the 8061 there are ONLY AD0 .. AD7 none of the "other" address lines so ...
when the 8061 wants to read an address it must
1) present 8 bits of the address and send the latch signal
2) present the OTHER 8 bits of the address and send the latch
3) enable the "Read Enable" flag, and read the 8 data bits

Just about everything you could want to know about the J3 port - http://binary.uta.edu/EEC/March/index.html
A J3 socket eprom adapter using 74 series logic devices - http://binary.uta.edu/EEC/March/J3%20adapter/j3.pdf
Or using a PLD - http://binary.uta.edu/EEC/March/J3%20ad ... 3adapt.htm

As I've said before...
Your far too smart for me even thinking I could do a 1/4 of what you do!

Thanks heaps for the insight!