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The controller ic was pulled from a gameboy cart which is more or less ideal for this use. It disables /CE below around 4v and switches to battery power below 3v. It also has a gated input to control /CE from the cpu when the supply is > 4v. This *should* work but still corrupts the data.

Maybe try putting a jumper in the /WE line so you can fire it up with the ecu's /WE isolated from the sram, and if that boots without corrupting it then fit the jumper while logging and see if it instantly breaks or not?
Any idea what the PM ic is?

It fails even with /WE tied high, something else going on i'm sure.

http://www.chinaeds.com/zl/Laoli%5CM%5C ... mm1134.pdf is the link to the PM ic. I've viewed the waveforms in and out of this chip and seems to be doing what I want.

I've just captured a few traces with various reads and writes, I'll post the pics in a second

That datasheet looks like it doesnt gate ce, it controls it itself?
And is pin 7 /Y connected to D5 on the sram?

Above is a typical read bus transaction. OE and CE are as measured on the EPROM's pins, the A15 is taken from the PCB as are the other signals.

The RW line is active much of the time because it is this signal that enables writing to other chips on the bus, not just our NVRAM. You can also see NVRAM /CS is not active during these writes. /OE is always active on the NVRAM. Also worth noting is that the NVRAM is only read when A15 is high, indicating it resides in the upper 32kbytes of addressable ROM Space (0x8000 - 0xFFFF). The 'E' signal is the CPU's enable or synchronisation signal. This is what we'll use for the FRAM.
In this snapshot, we can see a byte write to the NVRAM. A15 is high, indicating the NVRAM is being addressed. WR drops low to initiate a write and then /CE drops low to activate the NVRAM. The problem here is that /OE is still active.

This raises the question, How is NVRAM being written to when the waveforms are so far off the signaling spec.

festy wrote:That datasheet looks like it doesnt gate ce, it controls it itself?
And is pin 7 /Y connected to D5 on the sram?

I had a good play with CE & /CE. The datasheet is incorrect in its operation which I suppose is not a big surprise. /CE will track /Y unless VCC drops enough to activate the under voltage protection. /CE is then driven high by Vbatt.

What is /Y connected to? It looks like pin 17 on the sram from what I can make out in your photo

/Y is connected to /CS of the EPROM socket.

BennVenn wrote:It was mentioned earlier in this thread that EPROM /CE is tied low permanently. This is not true. EPROM /OE is pulled low and /CE is switched via the CPU.

Why do you say that? Pin 14 on the memcal socket is /CE, and there's a 10k resistor to ground on the bottom of the board.
Memcal socket pin 18 is /OE and is connected to pin 20 (/ROMOE) on the MCU.

edit - i see the confusion, MCU OE drives eprom CE.

BennVenn wrote:
In this snapshot, we can see a byte write to the NVRAM. A15 is high, indicating the NVRAM is being addressed. WR drops low to initiate a write and then /CE drops low to activate the NVRAM. The problem here is that /OE is still active.

This raises the question, How is NVRAM being written to when the waveforms are so far off the signaling spec.

From the datasheet:

Maxim wrote: WRITE MODE
The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE
will disable the outputs in tODW from its falling edge.

The write timing diagrams don't show /OE at all, it looks like holding /OE low permanently is still within spec for writes?