Processor architecture definition

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Witrenko
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Processor architecture definition

Post by Witrenko »

I have an old Audi A6 from 1996, the computer on it is MSA 11 or it is also called edc 1.3.1
I want to install a turbine with geometry, but first I need to change the Map sensor, do linearization, I can't figure out where the multiplier is, because I found the 2D linearization map itself 6B20
And much more, but first of all you need to determine the manufacturer and architecture of this old processor.
I know for sure that it is 8 bit, but when loading into Ghydra you can only select 16 bit processors
Don't tell me clever programming terms, I'm 0, I just work at WinOlss

I am attaching a file with a photo of the processor and the ECU itself
And two firmware files for the car,
the first ...328 for fuel supply
the second ...329 for boost and SOI

Please be understanding of the kettle.
Thank you
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antus
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Re: Processor architecture definition

Post by antus »

It looks like intel 8051. This is the turbo file loaded at 0x0000 and with default configuration in ida. It was an educated guess from it saying intel on the chip and '80 maybe 1980s processor.
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Witrenko
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Re: Processor architecture definition

Post by Witrenko »

I ask for help in further work on the file, I downloaded it, did the analysis.
Analiz .jpg
In the list you can see two links (0x6B22 indefikator), (0x6B25 Z axis)
Xped .jpg
I go to them, and I don't see any multiplier.
Why am I looking for multipliers
Because I read the forums:
https://www.ecuconnections.com/forum/vi ... 778#p58778
https://www.ecuconnections.com/forum/vi ... 200#p58870
Which say that:
- 18 in the kwp1281 protocol is equal to 0.04 x A x B.....so 0.04 X 255 x 255 = 2602.
Is it possible that my ECU works according to a different algorithm.
Thanks
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Witrenko
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Re: Processor architecture definition

Post by Witrenko »

BEHIND the address (0x6B25 ) is a link to:
Jump 1.jpg
Then to - TF0_Timer_vector_0:
Jump 2.jpg
I go to Graph, and I don't see any multiplier.
Graph .jpg
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antus
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Re: Processor architecture definition

Post by antus »

Usually on these low power systems they try to avoid multiplication as an optimisation. Multiplication is a very costly, in terms of run time instruction. If they can use the raw value as it is they will, and they often use numbering systems where they can use bit shift to multiply or divide by 2 instead of running actual multiplication or division opcodes. Probably if you want to add a multiplier you'll need to add a new instruction. If you can use bit shifts instead that will be a safer way to go. Jump to unused code space, bitshift to say divide by 2 and jump back will use the minimum cpu time to achieve such a thing.
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AngelMarc
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Re: Processor architecture definition

Post by AngelMarc »

And I'll ad for clarity. 2 bit shift is 4x, 3 bit shift is 8x, 4 is 16x, 5 is 32x, etc.
In case that isn't clear to anybody.
Don't stress specific units.