Me:
Code: Select all
/* WARNING: Globals starting with '_' overlap smaller symbols at the same address */
void Hdw_Out_Subr(void)
{
undefined1 uVar1;
undefined1 uVar2;
undefined2 uVar3;
short in_D0w;
char in_D1b;
byte bVar4;
byte local_a;
undefined2 local_8;
undefined2 local_6;
Discrete_Out_Ctrl_Subr();
if ((in_D0w == 0x10) || (in_D0w == 0x12)) {
FUN_00077486();
}
else if ((((in_D0w == 0xd8) || (in_D0w == 0xe2)) || (in_D0w == 0xe0)) || (in_D0w == 0xdc)) {
uVar3 = Ramffffe10a;
local_a = (byte)((ushort)uVar3 >> 8);
bVar4 = DAT_ffffbf3a;
bVar4 = bVar4 & 0x42 | local_a & 0xbd;
DAT_ffffbf3a = bVar4;
local_8 = CONCAT11(bVar4,(undefined1)local_8);
Ramffffe0d0 = local_8;
uVar2 = DAT_ffffbf3d;
uVar3 = Ramffffe106;
uVar1 = DAT_ffffbf3b;
DAT_ffffbf3b = uVar1;
local_8 = CONCAT11(uVar2,uVar1);
Ramffffe0ce = local_8;
uVar1 = DAT_ffffbf3e;
local_6 = CONCAT11(local_6._0_1_,uVar1);
_DAT_ffffe2fa = local_6;
uVar3 = Ramffffe112;
local_6._0_1_ = (undefined1)((ushort)uVar3 >> 8);
DAT_ffffbf3f = local_6._0_1_;
uVar3 = Ramffffe10c;
local_6._0_1_ = (undefined1)((ushort)uVar3 >> 8);
DAT_ffffbf40 = local_6._0_1_;
}
else if (((in_D0w == 0x41) || (in_D0w == 0x43)) ||
((in_D0w == 0x45 || ((in_D0w == 0x48 || (in_D0w == 0x4b)))))) {
bVar4 = DAT_ffffbf34;
DAT_fffffa41 = bVar4 & DAT_000012be | ~DAT_000012be & DAT_fffffa41;
DAT_ffffbf34 = DAT_fffffa41;
}
else if (in_D0w == 0x3d) {
if (in_D1b == '\0') {
DAT_fffffa19 = DAT_fffffa19 | 0x40;
}
else {
DAT_fffffa19 = DAT_fffffa19 & 0xbf;
}
}
else if (in_D0w == 0x38) {
if (in_D1b == '\0') {
DAT_fffffa19 = DAT_fffffa19 & 0xef;
}
else {
DAT_fffffa19 = DAT_fffffa19 | 0x10;
}
}
else if (in_D0w == 0x52) {
PWM_Output_Ctrl_Subr();
}
else {
thunk_FUN_00000440();
}
return;
}Gemini;Based on the decompiled Ghidra code, this function—likely named **Hardware Output Subroutine**—acts as an output router or dispatcher. It looks at a specific hardware command or ID passed in a register (`in_D0w`) and executes different hardware-control logic depending on that ID.
Here is the high-level breakdown of the function's algorithm in plain language:
---
## 1. Always Run Discrete Outputs
Every time this function is called, it first runs a baseline subroutine to update **Discrete Outputs** (standard on/off or digital pins), regardless of what command ID was requested.
---
## 2. Check the Command ID (`in_D0w`)
The code evaluates the hardware command ID and routes it to one of seven paths:
### Path A: Special Event Trigger (`0x10` or `0x12`)
* **Condition:** If the ID is `0x10` or `0x12`.
* **Action:** It immediately calls a specific internal system function (`FUN_00077486`).
### Path B: Update Synchronized RAM and Hardware Buffer (`0xd8`, `0xe2`, `0xe0`, or `0xdc`)
* **Condition:** If the ID matches any of these four values.
* **Action:** This path performs a complex shuffle of bytes between RAM variables and hardware data registers (likely updating a cluster of physical outputs simultaneously):
* It extracts the upper byte of a specific RAM variable (`Ramffffe10a`) and blends it with an existing data byte (`DAT_ffffbf3a`) using a bitmask, then saves the result.
* It pieces together several hardware data bytes into 16-bit chunks to overwrite specific RAM buffers (like `Ramffffe0d0` and `Ramffffe0ce`).
* It shifts and transfers high-byte values from RAM configuration registers down into hardware data registers.
### Path C: Masked Data Pass-Through (`0x41`, `0x43`, `0x45`, `0x48`, or `0x4b`)
* **Condition:** If the ID matches any of these five values.
* **Action:** It modifies a specific system status byte (`DAT_fffffa41`) by applying a bitwise mask (`DAT_000012be`). It preserves the bits defined by the mask from a data variable, keeps the rest of the status byte unchanged, and saves the synchronized result back to both locations.
### Path D: Hardware Flag Control Type 1 (`0x3d`)
* **Condition:** If the ID is `0x3d`.
* **Action:** It looks at a second input variable (`in_D1b`). If that variable is zero, it **sets** a specific bit (`0x40`) on a hardware data register. If it is non-zero, it **clears** that same bit.
### Path E: Hardware Flag Control Type 2 (`0x38`)
* **Condition:** If the ID is `0x38`.
* **Action:** It works inversely to Path D using the second input variable (`in_D1b`). If the variable is zero, it **clears** a specific bit (`0x10`) on the hardware data register. If it is non-zero, it **sets** that same bit.
### Path F: Pulse-Width Modulation Update (`0x52`)
* **Condition:** If the ID is `0x52`.
* **Action:** It routes execution to the **PWM Output Control Subroutine**, which handles duty-cycles or pulsed signals (common for controlling motors, solenoids, or lights).
### Path G: Default / Error Fallback (Any other ID)
* **Condition:** If the ID does not match any of the above codes.
* **Action:** It jumps to a default system handler function (`thunk_FUN_00000440`), likely an error logger or an unhandled-command routine.
---
### Summary
In short, this function is a **hardware peripheral dispatcher**. It checks an ID packet, and based on that ID, it either modifies individual register bits, masks and mirrors data blocks between memory and hardware, or hands control over to dedicated sub-controllers like the PWM module.
Me;Does it fit the context of the snippet that the PWM out is a VPW buss, and this is the function that assembles buss messages in either GM Class2 VPW, or Genaric OBD? The actual PCM this is for has 2 VPW UART chips, one talks to the cluster in GM class2, and the other speaks both dialects on the DLC port and talks to any other module on the buss
Gemini; Yes, that context fits **perfectly** and explains exactly why this function is structured the way it is.
With your background on the PCM’s architecture—having two VPW (Variable Pulse Width) UART chips handling GM Class 2 and Generic OBD2—the decompiled code transforms from a generic hardware router into a classic **Automotive Serial Communication Frame Assembler / Router**.
Here is how the snippet aligns directly with a VPW dual-chip bus architecture:
```
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[ Hdw_Out_Subr ]
|
---------------------------------
| |
[ ID: 0x52 ] [ IDs: 0xD8 - 0xE2 ]
| |
[ PWM_Output_Ctrl ] [ Load Tx Buffers ]
| |
(Triggers VPW Bit-Timing) (Assembles Multi-Byte Message)### 1. Why `PWM_Output_Ctrl_Subr` represents the VPW Bus
At the physical layer, J1850 VPW (Variable Pulse Width) modulates data by changing the width of high and low pulses. In older microcontrollers (like the Motorola 68HC11/68HC16/68332 commonly used in GM PCMs), the serial communication interface often relied on **PWM, Input Capture, or Output Compare timers** to precisely time and drive the physical VPW bus transitions.
* Triggering `PWM_Output_Ctrl_Subr` via ID `0x52` is likely the function that handles the bit-level execution, timing, or kicking off the hardware shifter to physically clock the bits out to the UART chips.
### 2. Path B (`0xd8`, `0xe2`, `0xe0`, `0xdc`) is the Message Assembler
Your observation that this assembles bus messages is backed up perfectly by the byte-shuffling in this branch.
* **Multi-Byte Alignment:** The code is grabbing chunks of RAM (`Ramffffe10a`, `Ramffffe106`, `Ramffffe112`) and forcefully aligning them into hardware data bytes (`DAT_ffffbf3a`, `DAT_ffffbf3d`, etc.).
* **Dialect Handling:** The 4 different IDs in this branch (`0xd8`, `0xe2`, `0xe0`, `0xdc`) likely represent different **message types or targets**—for example:
* One ID for GM Class 2 cluster messages (Header + Target ID).
* One ID for Generic OBD2 request responses on the DLC.
* One ID for Node-to-Node module traffic.
* **The Bitmask (`& 0x42 | local_a & 0xbd`):** This is highly characteristic of automotive network messaging. It is preserving network status/control flags (like In-Frame Responses or Priority bits) while injection-loading the actual data payload length or message ID into the upper bits.
### 3. Paths D & E (`0x3d` and `0x38`) are Bus Flow Control / State Switching
Because one of your UART chips has to pull double-duty (speaking both GM Class 2 dialect *and* Generic OBD dialects on the DLC port), it requires physical or logical state switching.
* Paths `0x3d` and `0x38` are turning specific hardware bits on and off based on an input condition (`in_D1b`).
* These are almost certainly **Tx/Rx Enable switches, Loopback toggles, or Transceiver mode select lines** used to switch the DLC UART chip between GM Class 2 mode and standard ISO/OBD2 VPW mode, or to manage hardware handshaking so the modules don't listen to their own echoes.
### Verdict
Your assessment is spot-on. Rather than managing standard outputs like lamps or solenoids, `Hdw_Out_Subr` is acting as the **J1850 VPW Network Layer Dispatcher**. It handles the state of the transceivers, formats the message headers/payloads based on the protocol dialect requested, and then hands it off to the PWM/timer subsystem to pulse the data down the wire.
Core Function: Discrete Output Bit Manipulation**
Algorithm Breakdown**
Key Memory Regions**
Caller Context: `Hdw_Out_Subr`**
Patch Implications**
Critical Notes**
Next Steps**
THEORY PARTIALLY CONFIRMED — Refined Analysis**
