Couldnt really find a section for this..

[The1]

It's just a case of providing vcc and vss, the sclk and di/do lines, pin 6 and 7 pulled high, and ce is active high but needs to be cycled between each instruction.
I'm surprised that the 93c socket won't work, but it might have a hardwired ce line or something.

I've added ram write and eeprom store instructions to my code, so might try hand-editing a bin with hyperterm and calc tonight, to test my checksum theories before I worry about a frontend.

Sorry im new to all this still learning lots, i made up this socket with a header on the other end.

this is the pinouts for icsp?
http://www.batsocks.co.uk/readme/isp_headers.htm

So ive got iscp - chip
pin 1-3 di
pin 2-8 vcc
pin 4-8 gnd
pin 7-2 clk
pin 9-4 do

ce read store pins 1-6-7 need to pulled high, this means 5v to make it active? pull low would then be 0v?

IMAG0174.jpg (150.68 KiB) Viewed 5014 times

Dr Bob, thanks for posting the pics!!

[festy]

yes - high = 5v (via 10k resistor if possible) but the CE line can't be tied high - it needs to be pulled low between each instruction.

i.e. to read word 0:
pull CE high
send bits 1000011x so high DI, high clk, low clk, low di, high clk, low clk, high clk, low clk, high clk, low clk, high di, high clk, low clk, high clk, (last bit can be 1 or 0 so di doesn't matter) high clk, low clk
(that's the read instruction sent, now read data one bit at a time) read do, high clk, read do, low clk, high clk, read do, low clk, high clk, read do... until you've read all 16 bits
Then, low CE, and do it all again, to read word 1 is 1000111x... you get the idea

The CAT24C44 datasheet doesn't explicitly say the CE line has to be cycled per instruction, but alludes to it in the timing figures.
The X244C44 datasheet does spell out this requirement though.
I can't see any way to control CE via ICSP (maybe reset pin?) but I can try mine with CE tied high and see if it still works...

[festy]

I just tried a read with CE tied high, no go.
It will need to be switched per instruction. I checked the schematic for that DOS based programmer I posted a while ago, and it controls CE rather than tieing high too.

Sorry im new to all this still learning lots

you and me both - a few days ago I couldn't even spell SPI

[festy]

According to http://www.nbglin.com/download/eeprom.pdf the CE is pin 3 on the J5 header and active high (if that's the same as your board).
You'll also need to set the 24Cxx jumper to off, and 16bit on the other jumper.

[festy]

if i can get one of my programmers to read it ill post the file.

Rob

How is the unit powered? I was half expecting to see a battery in there, as 4 of the 5 pins on the connector are used for the nvram...
I'd be cautious about trying to read that IC too, the datasheet warns about improper socketing during pgm/verify operations causing damage.

[The1]

According to http://www.nbglin.com/download/eeprom.pdf the CE is pin 3 on the J5 header and active high (if that's the same as your board).
You'll also need to set the 24Cxx jumper to off, and 16bit on the other jumper.

yeh that seems to make more sense as i wasn't even getting 5v where it said on that other one i found, ive resoldered the wires and quick checked some of the circuit again the top left of that sheet and looks more promising, ive done a read now with the recall pin high and now im getting something.

[festy]

348982 kms?
If so, your read worked.

[The1]

yep that's it, and also i just tested writing to it, put the store recall pins on vcc as if ponyprog wasn't reading or write to it then there was only 300mv so it seems to enough to trigger a store, so now i guess i need another valid file to write and then ill fire it up.

[festy]

see if this one works, don't panic if the dash doesn't accept it though...

[The1]

didn't like that just gave me the error 555,555

Attached is another read 358,604

Ive put a socket on my test trip cluster unit so easy to test now

ive tested writing the old file back and swapping them over and it works so writing is definitely working!