FRAM NVRAM Board

[antus]

VL400 who created 12p originally said TBI wasnt supported in that code base, but Jayme tried it with acceptable results. But you need to be aware its less than ideal at the design phase.

[festy]

What's the one on the left? And its size?

It's off an '82 Alfa Spider that used a Bosch Jetronic FI.
I can't remember whether it's a Solex or Dell'Orto TB, but they're rare and expensive and don't have much going for them.

[BennVenn]

Just an update on the NVRAM. I decided to give the datasheet a good read and these chips need what is known as 'Precharge' which is a high on the /CE line before any read or write access. They also need /CE to be strobed for every address change. This is different to EPROM and SRAM where you can hold /CE low and control the IC via the /RD line.

I'm really hoping that the MCU toggles /CE every read/write access. If not I'll have to add a bit of logic to gate /CE with the system CLK.

I know the SIMTEK nvSRAM works flawlessly but they are rather expensive! Either way, I still have a batteryless NVRAM 808!

Super keen to get home and finish up the loom, install it and start it! I need to drive the car 100m down to the shed before I can pull the motor out and get all my PFI parts together.

[festy]

I looked into FRAM a few years ago but recall finding that the /CE timing was not compatible with the 808.

[BennVenn]

Do you know what brand/type/architecture the delco ECU is running? I'd like to dig a little deeper.

Festy, did you look at the data on an analyser/scope?

Worst case and CE is tied low most of the time, you can gate it with the system clock via a single AND gate and that will restore the signaling specs. It will be necessary to add some logic to ANY nvram to prevent corruption at powerdown/up.

[festy]

Worst case and CE is tied low most of the time

From memory, /CS is hard wired low and not driven by the MCU at all?

[BennVenn]

If there is more than 1 addressable device on the bus this is very unlikely, unless they are gating the /RD line through an IO controller... Antus says a separate IC controls spark and fuel timing which suggests a bus. Could easily be more than 1 though. I'll find out in a few hours!

Has anyone reversed the circuit at all?

[festy]

The peripherals are memory mapped, and /OE is used to (de)select the ROM.
Google "1227165 schematics" - it's the same as the 808 but has the SXR chip.

[BennVenn]

Thanks!!!! The injector driver looks like a peak+hold!! Must be because the TBI Injector will fail in a few min at 12v.

This means I can series up my low imp injectors and drive them directly (assuming there is no pintle detection) this just made my day!

[antus]

But how do you calibrate the dead time?