PCM Hammer P12 development

[Tazzi]

I dont see an issue with that... maybe add a couple dozen nops inbetween it?

[Gampy]

I have one out for testing that has a half dozen nop's between COP2 bset and bclr ...

[Tazzi]

I have one out for testing that has a half dozen nop's between COP2 bset and bclr ...

hmmm... wonder if theres a timer thats needing to be reset?? I feel like I came across this with the E40 stuff.... (which uses the same cpu)

[antus]

you might need to define them volatile so the compiler doesnt optimise them out thinking they are no-ops as you dont read them back. That will depend on compiler flags though. Disassemble your own code to see what actually came out of the compiler to validate function. Or, write the payload in assembler.

[Tazzi]

Looking at the processor data sheet, FA21 is port E output data register. Possibly if this is not being 'flicked' at the correct rate, this could be triggering something else to reset?

[kur4o]

In that FFFF0000 disassembly, where is the entry point, is it FF2000, so sub_FFFF2404 is the first code ran ??

There is no entry point. The pcm calls the subrutines pointers that are at the very start of ffff2000, depending on what data is sent to pcm.

[kur4o]

Pcm uses this line extensively, which is slightly different than bset and bclr.

eori.b #$80,(byte_FFFFFA21).w

With bset and bclr there is some timer code involved and reading some registers.

[antus]

eori is exclusive or, immediate. $80 is 1000 0000 eg bit 7. So each successive call like that will toggle bit 7 the other way, and leave the other bits untouched.

[Tazzi]

Pcm uses this line extensively, which is slightly different than bset and bclr.

eori.b #$80,(byte_FFFFFA21).w

With bset and bclr there is some timer code involved and reading some registers.

The timer is what Im worried about, I believe its be used in relations to interrupts firing thus might need to be manipulated?

[antus]

toggling all bits on one register and bit 7 on another is consistent with other m68k pcms. I think the second one could be an external hardware watchdog. That'd make more sense than being 2 performing exactly the same function on the same silicon, so if that register maps to a hardware port it would make sense. I guess you'd be able to see it on a logic analyzer if you could connect to the right pin.